This paper primarily focus on the examination of error that incorporated in datum during its transmission over the communication link. Thus, for improving steadiness and the quickness of error detection of data, it is needed to embed the examining property within the universal asynchronous receive/transmit (UART) chip. Implementation starts with the designing of basic UART module, multiple input signature register (MISR) and a comparator/tester individually using Verilog HDL. The whole design is now, assembled and upgrade for minimal on chip area with fast speed, simulated on Isim simulator, incorporate and checked on field programmable gate array (FPGA) to authenticate the design.